1. Field of the Invention
The present invention relates to a noise eliminating circuit for monitoring an input signal continuously within its operating period and identifying a noise component contained in the input signal for its elimination to provide a noise-free normal signal.
2. Description of the Related Art
When a pulse-like noise component narrow in width is mixed into an input signal which is entered into a control device such as a microcomputer or control equipment using a microcomputer, a malfunction may often occur in the control device. For this reason, the control device is usually provided with a noise eliminator for eliminating such a noise component from the input signal.
A conventional noise eliminator is illustrated in FIG. 1. This conventional noise eliminator is arranged to decide that an input signal having a pulse width less than 3 .mu.s is a noise component and eliminate it. The noise eliminator identifies an input signal alone that is greater than 3 .mu.s in width as a normal input signal and provides it as an output signal (FLOUT).
In FIG. 1, an input signal is sampled in synchronism with the rising edges of a clock signal CK of a cycle of 1 .mu.s and the samples of the input signal are sequentially held in edge-triggered type D flip-flop circuits (hereinafter a flip-flop circuit is abbreviated as an F/F) 1, 2 and 3 which are cascaded into a shift register.
When output signals N1, N2 and N3 of F/Fs 1, 2 and 3 are all at a logic "1" level as a result of sampling and holding of the input signal, this fact will indicate that the input signal was stable at a logic "1" level during three sampling intervals just before. Consequently the output (ALL1) of a logical product (AND) gate 4 having its input connected to the outputs of F/Fs 1, 2 and 3 goes to a logic "1" level, thereby causing an edge-triggered type JK F/F 5 to produce an output signal (FLOUT) at a logic "1" level.
On the other hand, when the outputs of F/Fs 1, 2 and 3 are all at a logic "0" level, it will indicate that the input signal was stably at a logic "0" level during three sampling intervals just before. As a result, the output (ALL0) of an AND gate 6 having its inputs connected to the inverted outputs of F/Fs 1, 2 and 3 goes to a logic "1" level, causing F/F 5 to produce an output signal at a logic "0" level.
When the outputs of F/Fs 1, 2 and 3 is in one of states other than (1, 1, 1) or (0, 0, 0), this means that the input signal was not in a stable state during those intervals. Since, under such a condition, the outputs of AND gates 4 and 6 are at a logic "0" level, the state of F/F 5 and thus its output signal do not change.
An operating waveform diagram of such a noise eliminator is illustrated in FIG. 2.
In FIG. 2, that waveform portion of the input signal (SIGN) indicated at A which is at a logic "1" level has an interval approximately equal to a period of four cycles of the clock signal (CK) and thus it is output as an output signal (FLOUT).
That waveform portion of the input signal indicated at B which is at a logic "1" level has an interval approximately equal to a period of one cycle of the clock signal and thus it is identified as a noise component and then eliminated so that it does not appear in the output signal.
However, when, like waveform portions as indicated at C, D, E and F, a noise component consisting of a train of pulses, which occur in succession over a period of time more than a period of three cycles of the clock signal and moreover in approximately the same cycle as the clock signal even if their respective widths (durations) are less than the clock signal period, is mixed into the input signal, a 1-level signal will appear in the output signal which has a duration approximately equal to a period of three cycles of the clock signal. This is due to the fact that the pulses indicated by waveform portions C, D, E and F were regarded as normal input signals although they were noise components to be eliminated. Thus, for such an input signal, the arrangement shown in FIG. 1 does not operate properly so as to meet requirements of a noise eliminator.
This is due to the fact that, in the arrangement of FIG. 1, the input signal is sampled in synchronism with the rising edges of the clock signal. That is, if narrow pulses occur intermittently which are at a logic "1" level or a logic "0" level at least when the clock signal rises, a noise component consisting of such narrow pulses will be identified as a normal signal that is continuous in level.